ВТ (непрофильный форум) > Уголок SUNтехника, SF 4800
Плата SB0 USIII+ 900 МГц, ошибки. РЕШЕНО
случайность:
плата SB0 USIII+ 900 МГц ошибки
При прогоне теста testboard sb0 визуально ошибок не видно
листинг теста
--- Цитировать ---sc1.YYY.ru:SC> testboard sb0
Loading the test table from board SB0 PROM 0 ...
{/N0/SB0/P2} Running CPU POR and Set Clocks
{/N0/SB0/P3} Running CPU POR and Set Clocks
{/N0/SB0/P2} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P3} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P2} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Running CPU POR and Set Clocks
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P1} Running CPU POR and Set Clocks
{/N0/SB0/P0} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P1} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P0} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P0} Running Basic CPU
{/N0/SB0/P1} Running Basic CPU
{/N0/SB0/P2} Running Basic CPU
{/N0/SB0/P0} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P0} Subtest: Display CPU Version, frequency
{/N0/SB0/P1} Subtest: Display CPU Version, frequency
{/N0/SB0/P3} Running Basic CPU
{/N0/SB0/P0} Version register = 003e0015.23000507
{/N0/SB0/P2} Subtest: Setting Fireplane Config Registers for aid 0x2
{/N0/SB0/P3} Subtest: Setting Fireplane Config Registers for aid 0x3
{/N0/SB0/P2} Subtest: Display CPU Version, frequency
{/N0/SB0/P3} Subtest: Display CPU Version, frequency
{/N0/SB0/P2} Version register = 003e0015.23000507
{/N0/SB0/P3} Version register = 003e0015.23000507
{/N0/SB0/P1} Version register = 003e0015.23000507
{/N0/SB0/P2} CPU features = 0000224f.004204ff
{/N0/SB0/P3} CPU features = 0000224f.004204ff
{/N0/SB0/P0} CPU features = 0000224f.004204ff
{/N0/SB0/P1} CPU features = 0000224f.004204ff
{/N0/SB0/P2} Ecache Control Register 00000000.07a34c00
{/N0/SB0/P3} Ecache Control Register 00000000.07a34c00
{/N0/SB0/P0} Ecache Control Register 00000000.07a34c00
{/N0/SB0/P2} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P1} Ecache Control Register 00000000.07a34c00
{/N0/SB0/P3} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P0} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P1} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P2} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P3} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P0} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P2} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} @(#) lpost 5.20.9 2008/02/26 13:13
{/N0/SB0/P3} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2008 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P2} Subtest: I-Cache RAM Test
{/N0/SB0/P3} Subtest: I-Cache RAM Test
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P0} Subtest: I-Cache RAM Test
{/N0/SB0/P1} Subtest: I-Cache RAM Test
{/N0/SB0/P0} Subtest: I-Cache TAGS Test
{/N0/SB0/P1} Subtest: I-Cache TAGS Test
{/N0/SB0/P2} Subtest: I-Cache TAGS Test
{/N0/SB0/P3} Subtest: I-Cache TAGS Test
{/N0/SB0/P0} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P1} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P2} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P3} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P0} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P1} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P2} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P3} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P0} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P1} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P2} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P3} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P0} Subtest: I-Cache Initialization
{/N0/SB0/P1} Subtest: I-Cache Initialization
{/N0/SB0/P2} Subtest: I-Cache Initialization
{/N0/SB0/P3} Subtest: I-Cache Initialization
{/N0/SB0/P0} Subtest: D-Cache RAM Test
{/N0/SB0/P1} Subtest: D-Cache RAM Test
{/N0/SB0/P2} Subtest: D-Cache RAM Test
{/N0/SB0/P3} Subtest: D-Cache RAM Test
{/N0/SB0/P2} Subtest: D-Cache TAGS Test
{/N0/SB0/P0} Subtest: D-Cache TAGS Test
{/N0/SB0/P1} Subtest: D-Cache TAGS Test
{/N0/SB0/P3} Subtest: D-Cache TAGS Test
{/N0/SB0/P0} Subtest: D-Cache MicroTags Test
{/N0/SB0/P1} Subtest: D-Cache MicroTags Test
{/N0/SB0/P2} Subtest: D-Cache MicroTags Test
{/N0/SB0/P3} Subtest: D-Cache MicroTags Test
{/N0/SB0/P0} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P1} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P2} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P3} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P0} Subtest: D-Cache Initialization
{/N0/SB0/P1} Subtest: D-Cache Initialization
{/N0/SB0/P2} Subtest: D-Cache Initialization
{/N0/SB0/P3} Subtest: D-Cache Initialization
{/N0/SB0/P0} Subtest: W-Cache RAM Test
{/N0/SB0/P1} Subtest: W-Cache RAM Test
{/N0/SB0/P2} Subtest: W-Cache RAM Test
{/N0/SB0/P0} Subtest: W-Cache TAGS Test
{/N0/SB0/P1} Subtest: W-Cache TAGS Test
{/N0/SB0/P2} Subtest: W-Cache TAGS Test
{/N0/SB0/P3} Subtest: W-Cache RAM Test
{/N0/SB0/P0} Subtest: W-Cache Valid bit Test
{/N0/SB0/P1} Subtest: W-Cache Valid bit Test
{/N0/SB0/P2} Subtest: W-Cache Valid bit Test
{/N0/SB0/P3} Subtest: W-Cache TAGS Test
{/N0/SB0/P0} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P1} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P2} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P3} Subtest: W-Cache Valid bit Test
{/N0/SB0/P0} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P1} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P2} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P3} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P0} Subtest: W-Cache Initialization
{/N0/SB0/P1} Subtest: W-Cache Initialization
{/N0/SB0/P0} Subtest: P-Cache RAM Test
{/N0/SB0/P1} Subtest: P-Cache RAM Test
{/N0/SB0/P2} Subtest: W-Cache Initialization
{/N0/SB0/P3} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P0} Subtest: P-Cache TAGS Test
{/N0/SB0/P1} Subtest: P-Cache TAGS Test
{/N0/SB0/P2} Subtest: P-Cache RAM Test
{/N0/SB0/P3} Subtest: W-Cache Initialization
{/N0/SB0/P0} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P2} Subtest: P-Cache TAGS Test
{/N0/SB0/P1} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P3} Subtest: P-Cache RAM Test
{/N0/SB0/P0} Subtest: P-Cache Status Data Test
{/N0/SB0/P1} Subtest: P-Cache Status Data Test
{/N0/SB0/P2} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P3} Subtest: P-Cache TAGS Test
{/N0/SB0/P0} Subtest: P-Cache Initialization
{/N0/SB0/P2} Subtest: P-Cache Status Data Test
{/N0/SB0/P3} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P1} Subtest: P-Cache Initialization
{/N0/SB0/P2} Subtest: P-Cache Initialization
{/N0/SB0/P3} Subtest: P-Cache Status Data Test
{/N0/SB0/P0} Subtest: Branch Prediction Initialization
{/N0/SB0/P1} Subtest: Branch Prediction Initialization
{/N0/SB0/P2} Subtest: Branch Prediction Initialization
{/N0/SB0/P3} Subtest: P-Cache Initialization
{/N0/SB0/P0} Subtest: IMMU Registers Access
{/N0/SB0/P1} Subtest: IMMU Registers Access
{/N0/SB0/P2} Subtest: IMMU Registers Access
{/N0/SB0/P3} Subtest: Branch Prediction Initialization
{/N0/SB0/P0} Subtest: DMMU Registers Access
{/N0/SB0/P1} Subtest: DMMU Registers Access
{/N0/SB0/P2} Subtest: DMMU Registers Access
{/N0/SB0/P3} Subtest: IMMU Registers Access
{/N0/SB0/P0} Subtest: 4M DTLB RAM Test
{/N0/SB0/P1} Subtest: 4M DTLB RAM Test
{/N0/SB0/P2} Subtest: 4M DTLB RAM Test
{/N0/SB0/P3} Subtest: DMMU Registers Access
{/N0/SB0/P0} Subtest: 8K DTLB RAM Test
{/N0/SB0/P2} Subtest: 8K DTLB RAM Test
{/N0/SB0/P3} Subtest: 4M DTLB RAM Test
{/N0/SB0/P1} Subtest: 8K DTLB RAM Test
{/N0/SB0/P2} Subtest: 4M DTLB TAG Test
{/N0/SB0/P3} Subtest: 8K DTLB RAM Test
{/N0/SB0/P2} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P0} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P3} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P1} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P2} Subtest: 8K DTLB TAG Test
{/N0/SB0/P3} Subtest: 4M DTLB TAG Test
{/N0/SB0/P2} Subtest: 4M ITLB RAM Test
{/N0/SB0/P3} Subtest: 8K DTLB TAG Test
{/N0/SB0/P0} Subtest: 4M DTLB TAG Test
{/N0/SB0/P1} Subtest: 4M DTLB TAG Test
{/N0/SB0/P0} Subtest: 8K DTLB TAG Test
{/N0/SB0/P1} Subtest: 8K DTLB TAG Test
{/N0/SB0/P2} Subtest: 8K ITLB RAM Test
{/N0/SB0/P3} Subtest: 4M ITLB RAM Test
{/N0/SB0/P0} Subtest: 4M ITLB RAM Test
{/N0/SB0/P1} Subtest: 4M ITLB RAM Test
{/N0/SB0/P2} Subtest: 4M ITLB TAG Test
{/N0/SB0/P3} Subtest: 8K ITLB RAM Test
{/N0/SB0/P0} Subtest: 8K ITLB RAM Test
{/N0/SB0/P1} Subtest: 8K ITLB RAM Test
{/N0/SB0/P2} Subtest: 8K ITLB TAG Test
{/N0/SB0/P3} Subtest: 4M ITLB TAG Test
{/N0/SB0/P0} Subtest: 4M ITLB TAG Test
{/N0/SB0/P1} Subtest: 4M ITLB TAG Test
{/N0/SB0/P2} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3} Subtest: 8K ITLB TAG Test
{/N0/SB0/P0} Subtest: 8K ITLB TAG Test
{/N0/SB0/P1} Subtest: 8K ITLB TAG Test
{/N0/SB0/P2} Subtest: E-Cache TAGS Test
{/N0/SB0/P0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P0} Subtest: E-Cache TAGS Test
{/N0/SB0/P1} Subtest: E-Cache TAGS Test
{/N0/SB0/P3} Subtest: E-Cache TAGS Test
{/N0/SB0/P2} Subtest: Fast Init. Verification Test
{/N0/SB0/P0} Subtest: Fast Init. Verification Test
{/N0/SB0/P1} Subtest: Fast Init. Verification Test
{/N0/SB0/P3} Subtest: Fast Init. Verification Test
{/N0/SB0/P2} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P3} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P0} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P1} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P2} Subtest: IMMU Initialization
{/N0/SB0/P0} Subtest: IMMU Initialization
{/N0/SB0/P1} Subtest: IMMU Initialization
{/N0/SB0/P2} Subtest: DMMU Initialization
{/N0/SB0/P3} Subtest: IMMU Initialization
{/N0/SB0/P2} Running FPU Tests
{/N0/SB0/P3} Running FPU Tests
{/N0/SB0/P0} Running FPU Tests
{/N0/SB0/P1} Running FPU Tests
{/N0/SB0/P0} Subtest: DMMU Initialization
{/N0/SB0/P1} Subtest: DMMU Initialization
{/N0/SB0/P0} Subtest: Map LPOST to local space
{/N0/SB0/P1} Subtest: Map LPOST to local space
{/N0/SB0/P0} Subtest: FPU Register Test
{/N0/SB0/P1} Subtest: FPU Register Test
{/N0/SB0/P2} Subtest: Map LPOST to local space
{/N0/SB0/P3} Subtest: DMMU Initialization
{/N0/SB0/P2} Subtest: FPU Register Test
{/N0/SB0/P3} Subtest: Map LPOST to local space
{/N0/SB0/P3} Subtest: FPU Register Test
{/N0/SB0/P0} Subtest: FSR Test
{/N0/SB0/P1} Subtest: FSR Test
{/N0/SB0/P2} Subtest: FSR Test
{/N0/SB0/P3} Subtest: FSR Test
{/N0/SB0/P0} Running Basic Ecache
{/N0/SB0/P1} Running Basic Ecache
{/N0/SB0/P2} Running Basic Ecache
{/N0/SB0/P0} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P3} Running Basic Ecache
{/N0/SB0/P1} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P2} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P3} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P0} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P1} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P2} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P3} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P0} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P1} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P2} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P3} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P0} Subtest: E-Cache Address Line Test
{/N0/SB0/P1} Subtest: E-Cache Address Line Test
{/N0/SB0/P2} Subtest: E-Cache Address Line Test
{/N0/SB0/P0} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P1} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Subtest: E-Cache Address Line Test
{/N0/SB0/P0} Subtest: E-Cache Initialization
{/N0/SB0/P2} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P1} Subtest: E-Cache Initialization
{/N0/SB0/P2} Subtest: E-Cache Initialization
{/N0/SB0/P3} Subtest: E-Cache Initialization
{/N0/SB0/P2} Running Memory Registers Tests
{/N0/SB0/P3} Running Memory Registers Tests
{/N0/SB0/P2} Subtest: Disable Memory Controllers
{/N0/SB0/P3} Subtest: Disable Memory Controllers
{/N0/SB0/P2} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P0} Running Memory Registers Tests
{/N0/SB0/P1} Running Memory Registers Tests
{/N0/SB0/P3} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P0} Subtest: Disable Memory Controllers
{/N0/SB0/P1} Subtest: Disable Memory Controllers
{/N0/SB0/P0} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P1} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P2} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P3} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P0} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P1} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P0} Running Memory Configuration Tests
{/N0/SB0/P1} Running Memory Configuration Tests
{/N0/SB0/P0} Subtest: Memory Controller Configuration
{/N0/SB0/P2} Running Memory Configuration Tests
{/N0/SB0/P1} Subtest: Memory Controller Configuration
{/N0/SB0/P3} Running Memory Configuration Tests
{/N0/SB0/P2} Subtest: Memory Controller Configuration
{/N0/SB0/P3} Subtest: Memory Controller Configuration
{/N0/SB0/P0} Subtest: Memory DIMMs Init
{/N0/SB0/P1} Subtest: Memory DIMMs Init
{/N0/SB0/P0} Subtest: UP Memory Clear
{/N0/SB0/P1} Subtest: UP Memory Clear
{/N0/SB0/P2} Subtest: Memory DIMMs Init
{/N0/SB0/P2} Subtest: UP Memory Clear
{/N0/SB0/P3} Subtest: Memory DIMMs Init
{/N0/SB0/P3} Subtest: UP Memory Clear
{/N0/SB0/P2} Running Memory Tests
{/N0/SB0/P3} Running Memory Tests
{/N0/SB0/P2} Subtest: Memory Addressing
{/N0/SB0/P0} Running Memory Tests
{/N0/SB0/P1} Running Memory Tests
{/N0/SB0/P3} Subtest: Memory Addressing
{/N0/SB0/P0} Subtest: Memory Addressing
{/N0/SB0/P1} Subtest: Memory Addressing
{/N0/SB0/P0} Subtest: Memory DIMM Access
{/N0/SB0/P0} Subtest: Memory MATS+
{/N0/SB0/P1} Subtest: Memory DIMM Access
{/N0/SB0/P2} Subtest: Memory DIMM Access
{/N0/SB0/P3} Subtest: Memory DIMM Access
{/N0/SB0/P1} Subtest: Memory MATS+
{/N0/SB0/P2} Subtest: Memory MATS+
{/N0/SB0/P3} Subtest: Memory MATS+
{/N0/SB0/P0} Subtest: Memory MARCH C-
{/N0/SB0/P0} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P0} Subtest: Enable Correctable Error Traps
{/N0/SB0/P2} Subtest: Memory MARCH C-
{/N0/SB0/P2} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P2} Subtest: Enable Correctable Error Traps
{/N0/SB0/P3} Subtest: Memory MARCH C-
{/N0/SB0/P3} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P3} Subtest: Enable Correctable Error Traps
{/N0/SB0/P1} Subtest: Memory MARCH C-
{/N0/SB0/P1} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P1} Subtest: Enable Correctable Error Traps
{/N0/SB0/P0} Running Ecache Functional
{/N0/SB0/P1} Running Ecache Functional
{/N0/SB0/P0} Subtest: E-Cache Functional
{/N0/SB0/P1} Subtest: E-Cache Functional
{/N0/SB0/P0} Subtest: E-Cache Stress
{/N0/SB0/P1} Subtest: E-Cache Stress
{/N0/SB0/P2} Running Ecache Functional
{/N0/SB0/P3} Running Ecache Functional
{/N0/SB0/P2} Subtest: E-Cache Functional
{/N0/SB0/P3} Subtest: E-Cache Functional
{/N0/SB0/P2} Subtest: E-Cache Stress
{/N0/SB0/P3} Subtest: E-Cache Stress
{/N0/SB0/P2} Running CPU Functional
{/N0/SB0/P3} Running CPU Functional
{/N0/SB0/P2} Subtest: IMMU Functional
{/N0/SB0/P0} Running CPU Functional
{/N0/SB0/P1} Running CPU Functional
{/N0/SB0/P3} Subtest: IMMU Functional
{/N0/SB0/P2} Subtest: DMMU Functional
{/N0/SB0/P3} Subtest: DMMU Functional
{/N0/SB0/P2} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P3} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P0} Subtest: IMMU Functional
{/N0/SB0/P1} Subtest: IMMU Functional
{/N0/SB0/P0} Subtest: DMMU Functional
{/N0/SB0/P1} Subtest: DMMU Functional
{/N0/SB0/P0} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P1} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P2} Subtest: I-Cache Functional
{/N0/SB0/P3} Subtest: I-Cache Functional
{/N0/SB0/P0} Subtest: I-Cache Functional
{/N0/SB0/P1} Subtest: I-Cache Functional
{/N0/SB0/P2} Subtest: I-Cache Parity Functional
{/N0/SB0/P3} Subtest: I-Cache Parity Functional
{/N0/SB0/P0} Subtest: I-Cache Parity Functional
{/N0/SB0/P1} Subtest: I-Cache Parity Functional
{/N0/SB0/P2} Subtest: I-Cache Parity Tag
{/N0/SB0/P3} Subtest: I-Cache Parity Tag
{/N0/SB0/P0} Subtest: I-Cache Parity Tag
{/N0/SB0/P1} Subtest: I-Cache Parity Tag
{/N0/SB0/P2} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P3} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P0} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P1} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P2} Subtest: D-Cache Functional
{/N0/SB0/P3} Subtest: D-Cache Functional
{/N0/SB0/P0} Subtest: D-Cache Functional
{/N0/SB0/P1} Subtest: D-Cache Functional
{/N0/SB0/P2} Subtest: D-Cache Parity Functional
{/N0/SB0/P3} Subtest: D-Cache Parity Functional
{/N0/SB0/P0} Subtest: D-Cache Parity Functional
{/N0/SB0/P1} Subtest: D-Cache Parity Functional
{/N0/SB0/P2} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P3} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P0} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P1} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P2} Subtest: W-Cache Functional
{/N0/SB0/P3} Subtest: W-Cache Functional
{/N0/SB0/P0} Subtest: W-Cache Functional
{/N0/SB0/P1} Subtest: W-Cache Functional
{/N0/SB0/P2} Subtest: P-Cache Functional
{/N0/SB0/P3} Subtest: P-Cache Functional
{/N0/SB0/P0} Subtest: P-Cache Functional
{/N0/SB0/P1} Subtest: P-Cache Functional
{/N0/SB0/P2} Subtest: FPU Functional
{/N0/SB0/P3} Subtest: FPU Functional
{/N0/SB0/P0} Subtest: FPU Functional
{/N0/SB0/P1} Subtest: FPU Functional
{/N0/SB0/P2} Subtest: FPU Functional Stress
{/N0/SB0/P3} Subtest: FPU Functional Stress
{/N0/SB0/P0} Subtest: FPU Functional Stress
{/N0/SB0/P1} Subtest: FPU Functional Stress
{/N0/SB0/P2} Subtest: Graphics Functional
{/N0/SB0/P3} Subtest: Graphics Functional
{/N0/SB0/P0} Subtest: Graphics Functional
{/N0/SB0/P1} Subtest: Graphics Functional
{/N0/SB0/P0} Running Advanced CPU Tests
{/N0/SB0/P1} Running Advanced CPU Tests
{/N0/SB0/P0} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P1} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P2} Running Advanced CPU Tests
{/N0/SB0/P3} Running Advanced CPU Tests
{/N0/SB0/P2} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P3} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P0} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P1} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P2} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P3} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P0} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P1} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P2} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P3} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P0} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P1} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P2} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P0} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P1} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P3} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P0} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P1} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P2} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P3} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P0} Subtest: FPU Move to Registers Test
{/N0/SB0/P1} Subtest: FPU Move to Registers Test
{/N0/SB0/P2} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P3} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P0} Subtest: FPU Branch Test
{/N0/SB0/P1} Subtest: FPU Branch Test
{/N0/SB0/P2} Subtest: FPU Move to Registers Test
{/N0/SB0/P3} Subtest: FPU Move to Registers Test
{/N0/SB0/P0} Subtest: Branch Memory Test
{/N0/SB0/P1} Subtest: Branch Memory Test
{/N0/SB0/P2} Subtest: FPU Branch Test
{/N0/SB0/P3} Subtest: FPU Branch Test
{/N0/SB0/P2} Subtest: Branch Memory Test
{/N0/SB0/P3} Subtest: Branch Memory Test
{/N0/SB0/P0} Subtest: CPU Stress
{/N0/SB0/P1} Subtest: CPU Stress
{/N0/SB0/P2} Subtest: CPU Stress
{/N0/SB0/P3} Subtest: CPU Stress
{/N0/SB0/P2} Running CPU ECC Tests
{/N0/SB0/P3} Running CPU ECC Tests
{/N0/SB0/P2} Subtest: Fast ECC errors test
{/N0/SB0/P3} Subtest: Fast ECC errors test
{/N0/SB0/P0} Running CPU ECC Tests
{/N0/SB0/P1} Running CPU ECC Tests
{/N0/SB0/P0} Subtest: Fast ECC errors test
{/N0/SB0/P1} Subtest: Fast ECC errors test
{/N0/SB0/P2} Subtest: MTAG ECC errors test
{/N0/SB0/P3} Subtest: MTAG ECC errors test
{/N0/SB0/P2} Subtest: SYSTEM ECC errors test
{/N0/SB0/P3} Subtest: SYSTEM ECC errors test
{/N0/SB0/P0} Subtest: MTAG ECC errors test
{/N0/SB0/P0} Subtest: SYSTEM ECC errors test
{/N0/SB0/P1} Subtest: MTAG ECC errors test
{/N0/SB0/P1} Subtest: SYSTEM ECC errors test
{/N0/SB0/P2} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P3} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P0} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P1} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P0} Running System Level Tests
{/N0/SB0/P1} Running System Level Tests
{/N0/SB0/P0} Subtest: MP Memory Access Test
{/N0/SB0/P2} Running System Level Tests
{/N0/SB0/P1} Subtest: MP Memory Access Test
{/N0/SB0/P3} Running System Level Tests
{/N0/SB0/P2} Subtest: MP Memory Access Test
{/N0/SB0/P3} Subtest: MP Memory Access Test
{/N0/SB0/P0} Subtest: Invalidate Caches
{/N0/SB0/P1} Subtest: Invalidate Caches
{/N0/SB0/P2} Subtest: Invalidate Caches
{/N0/SB0/P3} Subtest: Invalidate Caches
{/N0/SB0/P0} Running Board Memory Interleave
{/N0/SB0/P1} Running Board Memory Interleave
{/N0/SB0/P0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P1} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P2} Running Board Memory Interleave
{/N0/SB0/P3} Running Board Memory Interleave
{/N0/SB0/P2} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P3} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P0} Passed
{/N0/SB0/P1} Passed
{/N0/SB0/P2} Passed
{/N0/SB0/P3} Passed
sc1.YYY.ru:SC>
--- Конец цитаты ---
Но на плате горит оранжевый светодиод и зеленый, что обозначает какую то неисправность,
запустим команду showboards
--- Цитировать ---sc1.YYY.ru:SC> showboards
Slot Pwr Component Type State Status Domain
---- --- -------------- ----- ------ ------
SSC0 On System Controller Main Passed -
SSC1 On Present Spare - -
ID0 On Sun Fire 4800 Centerplane - OK -
PS0 On A153 Power Supply - OK -
PS1 On A153 Power Supply - OK -
PS2 Off No Grid Power - - -
FT0 On Fan Tray Low Speed OK -
FT1 On Fan Tray Low Speed OK -
FT2 On Fan Tray Low Speed OK -
RP0 On Repeater Board - OK -
RP2 On Repeater Board - OK -
/N0/SB0 On CPU Board V2 Assigned Degraded C
/N0/SB4 On CPU Board V2 Assigned Not tested C
/N0/IB6 On PCI I/O Board Assigned Not tested C
/N0/IB8 On PCI I/O Board Assigned Not tested C
--- Конец цитаты ---
это вывод до команды setkeyswitch on
случайность:
для того чтоб активировать всю систему
переходим в домен С
и вводим команду setkeyswitch on и домен С запускается
Можно вернуться в Platform Shell
По команде showboards можно увидеть следующее
--- Цитировать ---sc1.YYY.ru:SC> showboards
Slot Pwr Component Type State Status Domain
---- --- -------------- ----- ------ ------
SSC0 On System Controller Main Passed -
SSC1 On Present Spare - -
ID0 On Sun Fire 4800 Centerplane - OK -
PS0 On A153 Power Supply - OK -
PS1 On A153 Power Supply - OK -
PS2 Off No Grid Power - - -
FT0 On Fan Tray Low Speed OK -
FT1 On Fan Tray Low Speed OK -
FT2 On Fan Tray Low Speed OK -
RP0 On Repeater Board - OK -
RP2 On Repeater Board - OK -
/N0/SB0 On CPU Board V2 Active Degraded C
/N0/SB4 On CPU Board V2 Assigned Failed C
/N0/IB6 On PCI I/O Board Active Passed C
/N0/IB8 On PCI I/O Board Active Passed C
--- Конец цитаты ---
Плата SB0 уже активна, но у нее статус деградация. что не радует.
переползаем опять в консоль домена C
--- Цитировать ---sc1.YYY.ru:C> showboards
Slot Pwr Component Type State Status Domain
---- --- -------------- ----- ------ ------
/N0/SB0 On CPU Board V2 Active Degraded C
/N0/SB4 On CPU Board V2 Assigned Failed C
/N0/IB6 On PCI I/O Board Active Passed C
/N0/IB8 On PCI I/O Board Active Passed C
--- Конец цитаты ---
все тоже самое, только без остального железа
случайность:
В списке команд есть команда showcomponent, вот ей и поспользуюсь в консоли домена C
--- Цитировать ---sc1.YYY.ru:C> showcomponent
Component Status Pending POST Description
--------- ------ ------- ---- -----------
/N0/SB0/P0 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P1 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P2 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P3 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P0/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P0/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P0/B1/L1 disabled - chs 1024M DRAM
/N0/SB0/P0/B1/L3 disabled - chs 1024M DRAM
/N0/SB0/P1/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P1/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P1/B1/L1 enabled - pass 1024M DRAM
/N0/SB0/P1/B1/L3 enabled - pass 1024M DRAM
/N0/SB0/P2/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P2/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P2/B1/L1 enabled - pass 1024M DRAM
/N0/SB0/P2/B1/L3 enabled - pass 1024M DRAM
/N0/SB0/P3/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P3/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P3/B1/L1 enabled - pass 1024M DRAM
/N0/SB0/P3/B1/L3 enabled - pass 1024M DRAM
/N0/SB4/P0 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P1 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P2 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P3 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P0/B0/L0 enabled - untest empty
/N0/SB4/P0/B0/L2 enabled - untest empty
/N0/SB4/P0/B1/L1 enabled - untest empty
/N0/SB4/P0/B1/L3 enabled - untest empty
/N0/SB4/P1/B0/L0 enabled - untest empty
/N0/SB4/P1/B0/L2 enabled - untest empty
/N0/SB4/P1/B1/L1 enabled - untest empty
/N0/SB4/P1/B1/L3 enabled - untest empty
/N0/SB4/P2/B0/L0 enabled - untest 512M DRAM
/N0/SB4/P2/B0/L2 enabled - untest 512M DRAM
/N0/SB4/P2/B1/L1 disabled - chs 1024M DRAM
/N0/SB4/P2/B1/L3 disabled - chs 1024M DRAM
/N0/SB4/P3/B0/L0 enabled - untest 512M DRAM
/N0/SB4/P3/B0/L2 enabled - untest 512M DRAM
/N0/SB4/P3/B1/L1 enabled - untest 1024M DRAM
/N0/SB4/P3/B1/L3 enabled - untest 1024M DRAM
/N0/IB6/P0 enabled - pass IO Controller 0
/N0/IB6/P1 enabled - pass IO Controller 1
/N0/IB6/P0/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB6/P0/B1 enabled - untest 33MHz. PCI Bus
/N0/IB6/P1/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB6/P1/B1 enabled - untest 33MHz. PCI Bus
/N0/IB6/P0/B1/C0 enabled - untest 33MHz. 5V Short PCI card
/N0/IB6/P0/B1/C1 enabled - untest 33MHz. 5V Short PCI card
/N0/IB6/P0/B1/C2 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P0/B0/C3 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
/N0/IB6/P1/B1/C4 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P1/B1/C5 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P1/B1/C6 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P1/B0/C7 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
/N0/IB8/P0 enabled - pass IO Controller 0
/N0/IB8/P1 enabled - pass IO Controller 1
/N0/IB8/P0/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB8/P0/B1 enabled - untest 33MHz. PCI Bus
/N0/IB8/P1/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB8/P1/B1 enabled - untest 33MHz. PCI Bus
/N0/IB8/P0/B1/C0 enabled - untest 33MHz. 5V Short PCI card
/N0/IB8/P0/B1/C1 enabled - untest 33MHz. 5V Short PCI card
/N0/IB8/P0/B1/C2 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P0/B0/C3 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
/N0/IB8/P1/B1/C4 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P1/B1/C5 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P1/B1/C6 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P1/B0/C7 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
sc1.YYY.ru:C>
--- Конец цитаты ---
На плате SB0 проблемное место
/N0/SB0/P0/B1/L1 disabled - chs 1024M DRAM
/N0/SB0/P0/B1/L3 disabled - chs 1024M DRAM
случайность:
Чтоб убедиться что проблема в памяти а не в плате, поменял местами проблемные палки памяти D0, D1, D2, D3 банка B1 процессора P0 с процессором P1
На каждый процессор на плате установлено два банка по 4 палки.
Загрузил систему, и получил вот это
--- Цитировать ---sc1.YYY.ru:C> showcomponent
Component Status Pending POST Description
--------- ------ ------- ---- -----------
/N0/SB0/P0 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P1 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P2 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P3 enabled - pass UltraSPARC-III+, 900MHz, 8M ECache
/N0/SB0/P0/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P0/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P0/B1/L1 enabled - pass 1024M DRAM
/N0/SB0/P0/B1/L3 enabled - pass 1024M DRAM
/N0/SB0/P1/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P1/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P1/B1/L1 disabled - chs 1024M DRAM
/N0/SB0/P1/B1/L3 disabled - chs 1024M DRAM
/N0/SB0/P2/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P2/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P2/B1/L1 enabled - pass 1024M DRAM
/N0/SB0/P2/B1/L3 enabled - pass 1024M DRAM
/N0/SB0/P3/B0/L0 enabled - pass 1024M DRAM
/N0/SB0/P3/B0/L2 enabled - pass 1024M DRAM
/N0/SB0/P3/B1/L1 enabled - pass 1024M DRAM
/N0/SB0/P3/B1/L3 enabled - pass 1024M DRAM
/N0/SB4/P0 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P1 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P2 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P3 enabled - fail UltraSPARC-III+, 600MHz, 8M ECache
/N0/SB4/P0/B0/L0 enabled - untest empty
/N0/SB4/P0/B0/L2 enabled - untest empty
/N0/SB4/P0/B1/L1 enabled - untest empty
/N0/SB4/P0/B1/L3 enabled - untest empty
/N0/SB4/P1/B0/L0 enabled - untest empty
/N0/SB4/P1/B0/L2 enabled - untest empty
/N0/SB4/P1/B1/L1 enabled - untest empty
/N0/SB4/P1/B1/L3 enabled - untest empty
/N0/SB4/P2/B0/L0 enabled - untest 512M DRAM
/N0/SB4/P2/B0/L2 enabled - untest 512M DRAM
/N0/SB4/P2/B1/L1 disabled - chs 1024M DRAM
/N0/SB4/P2/B1/L3 disabled - chs 1024M DRAM
/N0/SB4/P3/B0/L0 enabled - untest 512M DRAM
/N0/SB4/P3/B0/L2 enabled - untest 512M DRAM
/N0/SB4/P3/B1/L1 enabled - untest 1024M DRAM
/N0/SB4/P3/B1/L3 enabled - untest 1024M DRAM
/N0/IB6/P0 enabled - pass IO Controller 0
/N0/IB6/P1 enabled - pass IO Controller 1
/N0/IB6/P0/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB6/P0/B1 enabled - untest 33MHz. PCI Bus
/N0/IB6/P1/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB6/P1/B1 enabled - untest 33MHz. PCI Bus
/N0/IB6/P0/B1/C0 enabled - untest 33MHz. 5V Short PCI card
/N0/IB6/P0/B1/C1 enabled - untest 33MHz. 5V Short PCI card
/N0/IB6/P0/B1/C2 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P0/B0/C3 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
/N0/IB6/P1/B1/C4 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P1/B1/C5 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P1/B1/C6 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB6/P1/B0/C7 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
/N0/IB8/P0 enabled - pass IO Controller 0
/N0/IB8/P1 enabled - pass IO Controller 1
/N0/IB8/P0/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB8/P0/B1 enabled - untest 33MHz. PCI Bus
/N0/IB8/P1/B0 enabled - untest 66/33MHz. PCI Bus
/N0/IB8/P1/B1 enabled - untest 33MHz. PCI Bus
/N0/IB8/P0/B1/C0 enabled - untest 33MHz. 5V Short PCI card
/N0/IB8/P0/B1/C1 enabled - untest 33MHz. 5V Short PCI card
/N0/IB8/P0/B1/C2 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P0/B0/C3 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
/N0/IB8/P1/B1/C4 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P1/B1/C5 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P1/B1/C6 enabled - untest 33MHz. 5V Long/Short PCI card
/N0/IB8/P1/B0/C7 enabled - untest 66/33MHz. 3.3V Long/Short PCI card
sc1.YYY.ru:C>
--- Конец цитаты ---
Ошибка перешла к процессору P1, значит точно память
случайность:
Так как у меня больше нет памяти то я вытащил исправные палки с другой платы
--- Цитировать ---/N0/SB4/P3/B1/L1 enabled - untest 1024M DRAM
/N0/SB4/P3/B1/L3 enabled - untest 1024M DRAM
--- Конец цитаты ---
Хотя во всей машине стоят палки по 512 Мб и логическйи банк должен быть 1024Мб, в этой плате часть памяти видна как 512Мб, с чем это связано пока не знаю.
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